![]() NOCP - Indicates that a Cortex-M coprocessor instruction was issued but the coprocessor wasĭisabled or not present.With the exception of Cortex-M0 MCUs, whether or not unaligned accesses below 4 bytes generate a fault is also configurable. Unaligned multiple word accesses, such as accessing a uint64_t that is not 8-byte aligned, will always generate this fault. UNALIGNED - Indicates an unaligned access operation occurred.DIVBYZERO - Indicates a divide instruction was executed where the denominator was zero.This register is a 2 byte register which summarizes any faults that are not related to memory access failures, such as executing invalid instructions or trying to enter invalid states. UsageFault Status Register (UFSR) - 0圎000ED2A Fields are only cleared by a system reset or by writing a 1 to them. NOTE: If multiple faults have occurred, bits related to several faults may be set. ![]() ![]() MemManage Status Register (MMFSR) - print/x *(uint8_t *)0圎000ED28.BusFault Status Register (BFSR) - print/x *(uint8_t *)0圎000ED29.UsageFault Status Register (UFSR) - print/x *(uint16_t *)0圎000ED2A.For example, in GDB it would look something like this: The register can be accessed via a 32 bit read at 0圎000ED28 or each register can be read individually. The register is comprised of three different status registers – UsageFault, BusFault & MemManage Fault Status Registers: This 32 bit register contains a summary of the fault(s) which took place and resulted in the exception. Relevant Status Registers Configurable Fault Status Registers (CFSR) - 0圎000ED28 NOTE: If you already know the state to inspect when a fault occurs, you may want to skip ahead to the section about how to automate the analysis. If you are trying to debug a Cortex-M0, you can skip ahead to the next section where we discuss how to recover the core register state and instruction being executed at the time of the exception. Recovering from a UsageFault without a SYSRESETĪll MCUs in the Cortex-M series have several different pieces of state which can be analyzed when a fault takes place to trace down what went wrong.įirst we will explore the dedicated fault status registers that are present on all Cortex-M MCUs except the Cortex-M0.Halting & Determining Core Register State.HardFault Status Register (HFSR) - 0圎000ED2C.Configurable Fault Status Registers (CFSR) - 0圎000ED28.
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